Let’s play with numbers

The study covered 88 CPU projects.

16 (18%) CPU have no license text and no license header in the files. To my opinion that makes them unusable, anyway most of them are also not active. In any case it show that the developer didn’t really care about how other could use his work.

At least 47 (53%) appear to be inactive. Most looks like design dropped here and forgotten. Well that’s life, but if you start a project with such core, you will end-up being your own support… not a comfortable place.

On the other hand, 24 (27%) looked really active with 13 (14%) being marked as ‘stable’ (whatever that means).

Let’s look at the category, I must admit that I didn’t fill the category for some inactive project as I didn’t look into enough detail to choose one. Also few projects are clones of legacy architecture, well this could be a category on its own…
So we have:

• 20 (22%) embedded CPU
• 1 (1%) high end CPU
• 3 (3%) portable CPU
• 41 (46%) tiny micro-controller
• the rest being unclassified for various reason stated above.

Well I guess my limit between embedded CPU and portable CPU is kind of subjective, I would say that embedded CPU don’t need and MMU nor 64bit data path.
Anyway That’s more embedded CPU than I though, I mean I had the impression to fill only tiny micro-controller, as many small project driven by one developer are just that anyway.

29 (32%) uses GCC or provide patch to GCC. (Some CPU are clone so they kind of have it for free). And most of the embedded CPU have gcc support, and all portable and high end CPU have too.
And most tiny micro-controller don’t use GCC, except mainly AVR clones. But that’s normal, most are programmed in assembly anyway, others are so simple that writing a compiler would be longer than writing the CPU !

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The study items are listed on the Open Source CPUs post, especially the category description.

I’m planning to finish the current list of processor projects on OpenCores. As the list is long and for most cpu all informations are likely to be present on the OpenCores page I will just add them to the summary table. I will silently discards the one without files, as those are just useless.

I’ve gone through the whole list, there was not much more to say about most CPU, but here are some thought.

ASPIDA sync/async DLX Core

It was long since I didn’t read about some asynchronous design, if your looking for that, it might be good for you 😉

JOP: a Java Optimized Processor

I’m more a C than Java programmer but his could be a nice stuff. Just a though if it is used for a smartphone/tablet it could require a kind of virtualization to run each app in a separate context… Maybe it’s already possible, I’ve not looked into the details.

MIPS: The legal risk.

While reading Yellow Star details I found an interesting letter from MIPS on Yellow Star’s page.
I was telling about my doubts with AVR clones, at least for MIPS this was clear (in 2002), they really did not like the clones at all!
So I guess MIPS is not an option unless they change their politics to win back some ARM market share…

As usual the summary table is there: Open Cpu Study Summary.

The study items are listed on the Open Source CPUs post, especially the category description.

Let’s have a look at OpenCores Certified processor Projects.
OpenRisc1000 is already done.

openMSP430

This is a clone of TI’s MSP430, a 16bit micro-controller. Just by this it’s a tiny micro-controller again…
Also it’s a clone again, there is a port of GCC for the MSP430 family: mspgcc.

Plasma

This on is a Mips-like, that is to say it has most MIPS I instructions except the patented one (the page says the patent expired, so one could probably add them, need to check the legal stuff, remember I’m no legal expert).
Well it work, is still serving a website so great 😉
It does not look like there is any MMU, so it’s an embedded CPU.

T400 µController

An implementation of a legacy cpu again… clone of National’s 4-bit COP400 microcontroller.
The distribution include a GPL V2 text but the header in the vhdl files does not refer to GPL but gives a rather more permissive licence (looks BSDish to me) especially allowing synthesized work to be distributed without the source…
As for the category, it’s a 4bit cpu remember, so a tiny micro-controller.

T48 µController

This is a MCS-48 microcontroller clone. The licence is the same as T400 above (it’s the same author).
A 8bit micro-controller that will continue to flood the tiny micro-controller category.

As usual the summary table is there: Open Cpu Study Summary.

The study items are listed on the Open Source CPUs post, especially the category description.

LEON 3

This is another well know GPL processor. With great resources and specific model for commercial use. The cpu is a 32bit SPARC V8 with caches, MMU and other high end features, I think it’s configurable enough to fall into my portable CPU category.

ZPU

It uses a BSD license for the HDL and a GPL for documentation, architecture and tools. Interesting choice to allow commercial hardware… Well let’s look into it: The ZPU is a zero operand, or stack based CPU, 32bit datapath, 8bit instruction set. As for the category, it looks like an embedded CPU, however the presentation claims it’s not targeted for running uCLinux, also remembering why Navré (see previous post on the topic) was started, ZPU is probably not powerful enough for this class, so it will be a tiny micro-controller.

AEMB

The AEMB instruction set is taken from Xilinx MicroBlase. The gcc toolchain is the one for the MicroBlase from xilinx, it does not look like it is in mainstream gcc. The AEMB license is GPL v3, it’s in beta state according to it’s page on opencores. It’s a 32bit RISC cpu, apparently able to run uCLinux, so it’s an embedded CPU.

OpenFire

There in an other project page on opencores (with no files) OpenFire.

The project looks stopped…
It’s another clone of the MicroBlase. It uses MIT license, so it’s free.

PacoBlase

To stay in xilinx cloned material. This is a rewritten PicoBlase implementation in modified BSD license. The project looks stopped (no update since may 2007).
It’s an 8bit micro-controller, the project also release an assembler for it KCAsm, It does not looks like there is any gcc available here. So we have yet another tiny micro-controller.

YASEP

Looks like an always in development CPU project. Licensed under GNU Affero General Public License version 3. It has it’s own assembler written in javascript.

I don’t know if this is still relevant but the obsolete page states the following:

If you’re brave enough, you can attempt to create a C compiler for YASEP, but this is a bit sarcastic. If you want to lose time, port GCC. But YASEP’s architecture does not suit C nor GCC well. In fact YASEP is designed to be programmed in assembly language, which is quite simple thanks to a barebone RISC approach. YASEP is a microcontroller, after all.

So gcc will probably never come for this CPU.
I see this project more like an architecture research than a really usable CPU, if you can’t write C at least for generic non over-optimized code, then it’s hard to port any existing software to it without much effort.
It also fall in the tiny micro-controller category.

CPU86

This comes with a GPL 2 license text but all cpu86 design files refer to LGPL 2,1+ in their headers… The CPU86 core is binary/instruction compatible with an iAPX8088 processor.
It’s probably only useful to update the hardware of a legacy system using 8088 CPU where nobody is able/willing to update the code that runs on it.
Well this don’t fit my categories 😉

Zet86

The goal of this project seams to rebuild a PC with open source hardware. It’s licensed under GPL version 3. It’s recent, and only implementing 16bit modes (ie 8088/80186).
This one also don’t really suit well with my categories…

So I’m done with the CPU currently listed on wikipedia’s soft microprocessor page.

As usual the summary table is there: Open Cpu Study Summary.

The study items are listed on the Open Source CPUs post, especially the category description.

OpenRisc

The goal of the project fits my view of open source hardware, nice 😉
They claim a stable status and both fpga and asic proven design, well after reading the OpenRisc 1000 is a family specification, so this really applies to the OR1200 which is the only actual implementation existing today. It’s a 32bit RISC CPU with Harvard architecture, caches and MMU.
So it fits in the portable CPU category.

OpenSparc

It really look like sun needed some publicity to me, anyway here it is, a strong high end CPU (8 cores 64bit Risc…) it’s released under GPL v2. I don’t know if oracle buying sun interfered here, but some link on the site were broken, and the data did not seam to be that recent… But if it’s stable they don’t need more releases. Finally it’s really too high end for any geeky project, but there is a more suitable fork: look at S1 Core.

Simply RISC S1 Core

This is a reduced version of OpenSparc T1 with a single core, so it’s still a powerful 64bit Risc, but I think it’s more accessible so it fits the portable CPU category.

Note: From the S1 Core project page on OpenCores the same maintainers started a new and similar project OpenSPARC-based SoC

A summary table including those CPU is available, currently only in OpenOffice Format: Open Cpu Study Summary.

I recently blogged about Open Source Hardware, lets take a look a bit more at the FPGA/ASIC kind of projects.

Any project big enough will require a CPU to control the rest of the hardware and maybe just run some user software. So we need an open source CPU ! That is to say, the code of a processor in a common HDL language (VHDL, verilog) with an open source licence.

A quick search on the internet and we have plenty of soft-processor, some open source, some not:

• Soft microprocessor on wikipedia
• Processor projects on OpenCores

So how do we compare all that ?

There is an interesting article on the subject on 1-code technologies: Soft CPU Cores for FPGA. It compares the cpu in terms of features and size (in FPGA cells).
(As too often on the internet it’s lacking a publication date so it’s hard to know how recent the information is.)

So I’m planning to review several CPU and publish my results.

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