First CPU review: OpenRisc, OpenSparc and S1 Core

The study items are listed on the Open Source CPUs post, especially the category description.


The goal of the project fits my view of open source hardware, nice 😉
They claim a stable status and both fpga and asic proven design, well after reading the OpenRisc 1000 is a family specification, so this really applies to the OR1200 which is the only actual implementation existing today. It’s a 32bit RISC CPU with Harvard architecture, caches and MMU.
So it fits in the portable CPU category.


It really look like sun needed some publicity to me, anyway here it is, a strong high end CPU (8 cores 64bit Risc…) it’s released under GPL v2. I don’t know if oracle buying sun interfered here, but some link on the site were broken, and the data did not seam to be that recent… But if it’s stable they don’t need more releases. Finally it’s really too high end for any geeky project, but there is a more suitable fork: look at S1 Core.

Simply RISC S1 Core

This is a reduced version of OpenSparc T1 with a single core, so it’s still a powerful 64bit Risc, but I think it’s more accessible so it fits the portable CPU category.

Note: From the S1 Core project page on OpenCores the same maintainers started a new and similar project OpenSPARC-based SoC

A summary table including those CPU is available, currently only in OpenOffice Format: Open Cpu Study Summary.